DocumentCode :
1316780
Title :
Very large scale integration (VLSI) implementation of low-complexity variable block size motion estimation for H.264/AVC coding
Author :
Hsia, Shih-Chang ; Hong, P.-Y.
Author_Institution :
Dept. of Electron. Eng., Nat. Kaohsiung First Univ. of Sci. & Technol., Kaohsiung, Taiwan
Volume :
4
Issue :
5
fYear :
2010
fDate :
9/1/2010 12:00:00 AM
Firstpage :
414
Lastpage :
424
Abstract :
This study presents a fast algorithm and its very large scale integration (VLSI) design to implement the variable block size motion estimation. The fast algorithm is proposed with a hardware-oriented concept for regular VLSI design. Simulations show that the proposed algorithm can reduce about 90% motion searching time, whereas PSNR only decreases about 0.02 dB on average. Based on the fast algorithm, VLSI architecture is designed with parallel structure and pipeline timing schedule to achieve high throughput rate for the HDTV system. The chip can compute 41 vectors for various block size during 24-240 cycles as using only 96 processing elements. Comparisons with contemporary VLSI architectures, this chip can offer higher processing speed, wider searching range and lower circuit complexity.
Keywords :
VLSI; circuit complexity; high definition television; logic design; motion estimation; pipeline processing; video coding; H.264/AVC coding; HDTV system; VLSI architecture; VLSI design; circuit complexity; hardware-oriented concept; low-complexity variable block size motion estimation; motion searching time; parallel structure; pipeline timing schedule; throughput rate;
fLanguage :
English
Journal_Title :
Circuits, Devices & Systems, IET
Publisher :
iet
ISSN :
1751-858X
Type :
jour
DOI :
10.1049/iet-cds.2009.0200
Filename :
5567025
Link To Document :
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