Differential-read symmetrical 8T SRAM bit-cell with enhanced data stability

A simple but novel 8-transistor (8T) SRAM cell with enhanced data stability is presented. During a read operation, the proposed cell suppresses a noise-vulnerable `0` node rising, and hence exhibiting a near-ideal butterfly curve essential for robust bit-cell design. The cell itself bears improved variability tolerance which gives much tighter stability distribution across skewed process corners. Implementation results in a 0.13``m CMOS technology show that the proposed 8T cell achieves `100` higher read stability compared to the conventional 6T cell. The data write-ability and stability tolerance provided with the new cell are also verified under process variations.