Title :
Floating-gate CMOS ternary latch
Author :
De la Cruz Blas, Carlos A. ; Green, Michael M.
Author_Institution :
Dept. of Electr. & Electron. Eng., Public Univ. of Navarre, Pamplona, Spain
fDate :
9/1/2010 12:00:00 AM
Abstract :
The design of a novel floating-gate CMOS ternary latch is presented. The design is based on a CMOS latch with level shifters that are realised using floating-gate techniques. The three stable operating points possessed by this circuit allow the cell to realise a ternary latch. The number of operating points possessed by the latch can be set using an external DC voltage. Measurement results from a fabricated prototype in a 0.5 m CMOS technology are included to demonstrate the design presented.
Keywords :
CMOS integrated circuits; flip-flops; semiconductor device models; CMOS ternary latch; DC voltage; floating gate technique; level shifter; size 0.5 micron;
Journal_Title :
Electronics Letters
DOI :
10.1049/el.2010.2004
