Title :
Panning sorter: An approach to the design of minimal-hardware parallel-input data sorters
Author :
Pedroni, Volnei A. ; Jasinski, R.P. ; Pedroni, R.U.
Author_Institution :
Dept. of Electron. Eng., UTFPR, Curitiba, Brazil
fDate :
9/1/2010 12:00:00 AM
Abstract :
The panning sorter is introduced, offering a new approach to the design of highly compact digital parallel-input sorters for low power 2D applications, such as image processing and data switching, among others. The result is believed to be the smallest sorter circuit for this type of implementation, for the given time complexity.
Keywords :
image processing; sorting; data switching; image processing; low power 2D applications; minimal-hardware parallel-input data sorters; panning sorter; sorter circuit; time complexity;
Journal_Title :
Electronics Letters
DOI :
10.1049/el.2010.1568
