DocumentCode
1317144
Title
Proposal for a versatile monolithic multi-Gbit/s m-sequence test system
Author
Bussmann, Michael ; Langmann, U.
Author_Institution
Ruhr-Univ. Bochum, Mikroelektronik-Zentrum, West Germany
Volume
26
Issue
19
fYear
1990
Firstpage
1625
Lastpage
1626
Abstract
A multi-functional system is proposed which combines four important features for m-sequence applications: generation of m-sequences, detection of bit errors, derivation of word synchronisation pulses, and scrambling as well as descrambling of a data stream. Circuit simulations show that a monolithic realisation for data rates of more than 10 Gbit/s is feasible using a simple self-aligning Si bipolar technology.
Keywords
binary sequences; bipolar integrated circuits; digital integrated circuits; elemental semiconductors; emitter-coupled logic; shift registers; silicon; test equipment; 10 Gbit/s; Si circuits; derivation of word synchronisation pulses; descrambling; detection of bit errors; features; m-sequence generation; maximum length sequence generator; monolithic realisation; multi-Gbit/s m-sequence test system; multi-functional system; pseudorandom binary sequence generator; scrambling; semiconductors; simple self-aligning Si bipolar technology;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:19901041
Filename
83073
Link To Document