DocumentCode
1317358
Title
Reliability Analysis of Logic Circuits
Author
DesMarais, P. ; Krieger, Michael
Author_Institution
Dept. of Electrical Engineering/University of Ottawa/Ottawa, Ontario K1N 6N5 CANADA
Issue
1
fYear
1975
fDate
4/1/1975 12:00:00 AM
Firstpage
46
Lastpage
52
Abstract
An efficient algorithm is presented for computing the reliability matrix of a logic network whose components are characterized by a known probability of malfunctioning. Using the concept of path sensitizing, a graphical representation of error propagation is derived. Through the computation of Boolean path functions, the information provided by these graphs is put into a malfunction table from which the matrix entries are directly computed. The method not only offers computational efficiency but also provides further physical insight into the reliability problem.
Keywords
Boolean algebra; Circuit analysis; Circuit analysis computing; Computational efficiency; Computer networks; Fault tolerance; Intersymbol interference; Logic circuits; Sequential circuits; Stochastic processes;
fLanguage
English
Journal_Title
Reliability, IEEE Transactions on
Publisher
ieee
ISSN
0018-9529
Type
jour
DOI
10.1109/TR.1975.5215328
Filename
5215328
Link To Document