Title :
Nanoscale ultra-thin-body silicon-on-insulator P-MOSFET with a SiGe/Si heterostructure channel
Author :
Yee Chia Yee ; Subramanian, Vivek ; Kedzierski, Jakub ; Xuan, Peiqi ; King, Tsu-Jae ; Bokor, Jeffrey ; Hu, Chenming
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
fDate :
4/1/2000 12:00:00 AM
Abstract :
We report the concept and demonstration of a nanoscale ultra-thin-body silicon on-insulator (SOI) P-channel MOSFET with a Si/sub 1-x/Ge/sub x//Si heterostructure channel. First, a novel lateral solid-phase epitaxy process is employed to form an ultra-thin-body that suppresses the short-channel effects. Negligible threshold voltage roll-off is observed down to a channel length of 50 nm. Second, a selective silicon implant that breaks up the interfacial oxide is shown to facilitate unilateral crystallization to form a single crystalline channel. Third, the incorporation of SiGe in the channel resulted in a 70% enhancement in the drive current.
Keywords :
Ge-Si alloys; MOSFET; nanotechnology; silicon; silicon-on-insulator; solid phase epitaxial growth; 50 nm; SOI P-MOSFET; SiGe-Si; SiGe/Si heterostructure channel; drive current enhancement; interfacial oxide; lateral solid-phase epitaxy process; nanoscale ultra-thin-body PMOSFET; p-channel MOSFET; selective Si implant; short-channel effect suppression; single crystalline channel; threshold voltage rolloff; unilateral crystallization; Crystallization; Epitaxial growth; Fluctuations; Germanium silicon alloys; Implants; MOSFET circuits; Semiconductor films; Silicon germanium; Silicon on insulator technology; Threshold voltage;
Journal_Title :
Electron Device Letters, IEEE