• DocumentCode
    1317633
  • Title

    Isolation edge effect depending on gate length of MOSFETs with various isolation structures

  • Author

    Oishi, Toshiyuki ; Shiozawa, Katsuomi ; Furukawa, Akihiko ; Abe, Yuji ; Tokuda, Yasunori

  • Author_Institution
    Adv. Technol. R&D Center, Mitsubishi Electr. Corp., Hyogo, Japan
  • Volume
    47
  • Issue
    4
  • fYear
    2000
  • fDate
    4/1/2000 12:00:00 AM
  • Firstpage
    822
  • Lastpage
    827
  • Abstract
    The gate length (L) dependence of the isolation edge effect is investigated for MOSFETs with various isolation structures. We extract the isolation edge effect for a single L by comparing with an H-shaped gate MOSFET which did not have any influence from the isolation edges. For shallow trench isolation (STI), the isolation edge effect is enhanced for L around the onset of the short channel effect (SCE) and is more prominent for a trench edge with a deeper dip. On the other hand, for the local oxidation of silicon (LOCOS) isolation with an elevated field oxide edge (i.e., the bird´s beak), the isolation edge effect operates in the opposite direction against the cases of STI, though it is enhanced around the SCE appearance point. The L dependence is successfully explained using the charge sharing model where the charge shared by the mixing effect between the SCE and the (inverse) narrow width effect [(I)NWE] is introduced at the channel corners. The enhancement of the isolation edge effect results from that the fraction of the charge shared by the mixing effect depends on L. In addition, the difference between STI and LOCOS occurs because the mixing effect for STI is opposite to that for LOCOS
  • Keywords
    MOSFET; isolation technology; LOCOS; MOSFET; bird´s beak; charge sharing model; gate length dependence; inverse narrow width effect; isolation edge effect; mixing effect; narrow width effect; shallow trench isolation; short channel effect; Electric variables; Helium; Isolation technology; MOSFET circuits; Oxidation; Research and development; Shape; Silicon; Threshold voltage; Ultra large scale integration;
  • fLanguage
    English
  • Journal_Title
    Electron Devices, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9383
  • Type

    jour

  • DOI
    10.1109/16.830999
  • Filename
    830999