Trading-off programming speed and current absorption in flash memories with the ramped-gate programming technique

This work studies the trade-off between programming speed and current absorption in flash EEPROM memories that can be achieved using a ramped-gate programming (RGP) method. The writing parallelism as a function of the programming speed is discussed and it is shown how the flexibility of the RGP scheme can be effectively used to meet very different programming requirements. In particular, the results of this paper address two significant applications: a highly parallel (2 K cells) soft-programming procedure able to remarkably tighten erased V _T distribution and a multilevel, high bandwidth (1 Mbytes/s) programming operation. For both applications, the most relevant issues for a practical use are discussed, such as the choice of drain and substrate voltages in relation to current absorption, the statistical distribution of programmed threshold voltages, and the endurance characteristics