Trading-off programming speed and current absorption in flash memories with the ramped-gate programming technique

Author

Esseni, David ; Villa, C. ; Tassan, S. ; Riccó, Bruno

Author_Institution

Lucent Technol., AT&T Bell Labs., Murray Hill, NJ, USA

Volume

47

Issue

4

fYear

2000

fDate

4/1/2000 12:00:00 AM

Firstpage

828

Lastpage

834

Abstract

This work studies the trade-off between programming speed and current absorption in flash EEPROM memories that can be achieved using a ramped-gate programming (RGP) method. The writing parallelism as a function of the programming speed is discussed and it is shown how the flexibility of the RGP scheme can be effectively used to meet very different programming requirements. In particular, the results of this paper address two significant applications: a highly parallel (2 K cells) soft-programming procedure able to remarkably tighten erased V _T distribution and a multilevel, high bandwidth (1 Mbytes/s) programming operation. For both applications, the most relevant issues for a practical use are discussed, such as the choice of drain and substrate voltages in relation to current absorption, the statistical distribution of programmed threshold voltages, and the endurance characteristics

Keywords

PLD programming; flash memories; integrated memory circuits; EEPROM memories; current absorption; drain voltage selection; endurance characteristics; flash memories; highly parallel soft-programming procedure; multilevel high bandwidth programming operation; programmed threshold voltages; programming speed; ramped-gate programming technique; substrate voltage selection; writing parallelism; Absorption; Bandwidth; Electrons; Flash memory; Functional programming; Parallel programming; Random access memory; Statistical distributions; Threshold voltage; Voltage control;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.831000

Filename

831000