Thermal-Aware Energy Optimization by Synthesizing Firm 3-D Network-on-Chip with Voltage-Frequency Islands

In this paper, we introduce voltage-frequency island (VFI) -based design paradigm into three dimensional (3-D) network-on-chip (NoC) to optimize system energy. The prominent challenges to VFI-based 3-D NoC designs are the exacerbated thermal issues. Moreover, targeting hard platform with pre-designed structure restrains the optimization space of the prior work. In view of the above limitations, we propose a VFI-aware synthesis framework to minimize system energy and keep thermal balancing for the firm 3-D NoC platform where designers have the freedom to make mapping decisions on computation components. Besides task scheduling and voltage scaling for computation energy minimization, core stacking and task migrating algorithm are proposed to optimize communication energy and balance powers across the core stacks. By treating each core stack as a unity, VFI aware 3-D NoC mapping problem can be simplified as the mapping issue on 2-D. Experimental results demonstrate that on average our framework can achieve an energy reduction of 18.6% over the prior thermal balancing algorithm. Moreover, on average 5.7 °C reduction in peak temperature is achieved by our framework, compared with the state-of-art energy optimization scheme.