RF potential of a 0.18-μm CMOS logic device technology

Author

Burghartz, Joachim N. ; Hargrove, Michael ; Webster, Charlers S. ; Groves, Robert A. ; Keene, Michael ; Jenkins, Keith A. ; Logan, Ronald ; Nowak, Edward

Author_Institution

DIMES, Delft Univ. of Technol., Netherlands

Volume

47

Issue

4

fYear

2000

fDate

4/1/2000 12:00:00 AM

Firstpage

864

Lastpage

870

Abstract

The radio-frequency (RF) performance of a 0.18-μm CMOS logic technology is assessed by evaluating the cutoff and maximum oscillation frequencies (f_T and f_max), the minimum noise figure (F_min) and associated power gain (G_a), and the 1/f noise of the devices. Gate-biasing and channel-length and gate-finger-length adjustments are identified as means to optimize the RF performance without any technology process modifications. Changing to N₂O gate dielectrics is shown to greatly reduce the 1/f noise without sacrificing the AC performance. The power amplifier characteristics of CMOS at low power levels are also discussed

Keywords

1/f noise; CMOS integrated circuits; UHF integrated circuits; UHF power amplifiers; dielectric thin films; integrated circuit noise; integrated circuit technology; low-power electronics; 0.18 micron; 1/f noise; CMOS logic device technology; N₂O; N₂O gate dielectrics; RF performance optimisation; channel-length adjustments; cutoff frequency; deep submicron CMOS technology; gate biasing; gate-finger-length adjustments; low power levels; maximum oscillation frequency; minimum noise figure; power amplifier characteristics; power gain; radiofrequency performance; CMOS logic circuits; CMOS technology; Cutoff frequency; Dielectrics; Logic devices; Noise figure; Noise reduction; Performance gain; Radio frequency; Radiofrequency identification;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.831006

Filename

831006