Title :
High speed latchup resistant CMOS data output buffer for submicrometre DRAM application
Author_Institution :
Dept. of Electron. Eng., Kangwon Nat. Univ., Chunchon, South Korea
fDate :
11/21/1996 12:00:00 AM
Abstract :
A latchup resistant CMOS data output buffer for 0.5 μm CMOS DRAM is designed, fabricated and measured. It has a floating n-well which adjusts its voltage level to suppress the leakage current. Its leakage current is controlled to be <10 nA with the bonding pad voltage ranging from 0 to 10 V. The propagation delay is measured to be shorter by 3.8 ns than that of an NMOS data output buffer
Keywords :
CMOS memory circuits; DRAM chips; buffer circuits; 0 to 10 V; 0.5 micron; DRAM; bonding pad voltage; floating n-well; high speed latchup resistant CMOS data output buffer; leakage current; propagation delay;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19961516
