A VLSI implementation of finite impulse response digital filters using residue number systems

An array architecture is presented for implementing a finite impulse response (FIR) digital filter in a residue number system (RNS). A FIR filter requires only the high speed residue operations, i.e. addition and multiplication. VLSI is used as a fabrication medium to support the modular implementation. A general computation element is proposed as a building block unit. It is a multi look-up table module whose function is determined by the programmed contents of its associated tables. The proposed array is based on the systolic concept which provides high throughput and simplicity offered by identical processing elements, all operating in parallel on data synchronously flowing through the structure. The proposed architecture lends itself to the pipelining systems. It offers most efficient performance for continuous input data stream applications. An example of implementing a 24th-order filter is also given. The performance measures (area and time) of this filter are analyzed based on a developed memory model.