DocumentCode
1319007
Title
Impact of technology trends on SEU in CMOS SRAMs
Author
Dodd, P.E. ; Sexton, F.W. ; Hash, G.L. ; Shaneyfelt, M.R. ; Draper, B.L. ; Farino, A.J. ; Flores, R.S.
Author_Institution
Sandia Nat. Labs., Albuquerque, NM, USA
Volume
43
Issue
6
fYear
1996
fDate
12/1/1996 12:00:00 AM
Firstpage
2797
Lastpage
2804
Abstract
The impact of technology trends on the SEU hardness of epitaxial CMOS SRAMs is investigated using three-dimensional simulation. We study trends in SEU susceptibility with parameter variations across and within technology generations. Upset mechanisms for various strike locations and their dependence on gate-length scaling are explored. Such studies are useful for technology development and providing input for process and design decisions. An application of SEU simulation, to the development of a 0.5-μm radiation-hardened CMOS SRAM is presented
Keywords
CMOS memory circuits; SRAM chips; integrated circuit technology; radiation hardening (electronics); 0.5 micron; SEU; epitaxial CMOS SRAM; gate-length scaling; radiation hardness; single event upset; technology trends; three-dimensional simulation; CMOS technology; Circuit simulation; Computational modeling; Doping profiles; Electric resistance; Equations; Iron; Random access memory; SPICE; Semiconductor process modeling;
fLanguage
English
Journal_Title
Nuclear Science, IEEE Transactions on
Publisher
ieee
ISSN
0018-9499
Type
jour
DOI
10.1109/23.556869
Filename
556869
Link To Document