Characterization of Electron Traps in Si-Capped Ge MOSFETs With $\hbox {HfO}_{2}/\hbox {SiO}_{2}$ Gate Stack

Si-capped Ge MOSFETs have good compatibility with existing processes, and promising results have been reported. The process is becoming sufficiently mature to warrant assessment of device reliability. Good time-dependent dielectric breakdown performance has been observed, and negative-bias-temperature-instability susceptibility is better than Si counterparts. Electron trapping is shown to be problematic and affects devices through positive bias temperature instability and hot carrier injection. This letter characterizes electron trapping in HfO₂/SiO₂ stacks on Si-capped Ge. Trapping is substantial, increasing with VG and reaching ~ 10¹³ cm^-2 in 100 μs under VG = 2.0 V. We report, for the first time, two distinctive capture cross sections (CCS) by measuring the transient gate current. The large CCS can be ~ 10^-12 cm² and reduces for a higher oxide field, which is a signature of coulombic attractive centers. The small CCS is on the order of 10^-14 cm², which is a typical value found for electron traps in SiO₂ and HfO₂/SiO₂ stacks on Si.