• DocumentCode
    1319895
  • Title

    Gate-level modeling of leakage current failure induced by total dose for the generation of worst-case test vectors

  • Author

    Abou-Auf, A.A.

  • Author_Institution
    US Army Res. Lab., Adelphi, MD, USA
  • Volume
    43
  • Issue
    6
  • fYear
    1996
  • fDate
    12/1/1996 12:00:00 AM
  • Firstpage
    3189
  • Lastpage
    3196
  • Abstract
    A novel gate-level model has been developed for the automatic generation of worst-case test vectors for leakage current failure induced in CMOS devices by total dose
  • Keywords
    CMOS logic circuits; VLSI; automatic testing; failure analysis; integrated circuit modelling; integrated circuit reliability; integrated circuit testing; leakage currents; radiation effects; CMOS devices; automatic generation; gate-level modeling; leakage current failure; total dose; worst-case test vectors; Automatic testing; Circuit testing; Fault diagnosis; Inverters; Leakage current; Logic testing; MOSFETs; SPICE; Semiconductor device modeling; Threshold voltage;
  • fLanguage
    English
  • Journal_Title
    Nuclear Science, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9499
  • Type

    jour

  • DOI
    10.1109/23.556924
  • Filename
    556924
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1319895