A 1.7 mW 11b 250 MS/s 2-Times Interleaved Fully Dynamic Pipelined SAR ADC in 40 nm Digital CMOS

Author

Verbruggen, Bob ; Iriguchi, Masao ; Craninckx, Jan

Author_Institution

imec, Leuven, Belgium

Volume

47

Issue

12

fYear

2012

Firstpage

2880

Lastpage

2887

Abstract

A 250 MS/s 2x interleaved 11 bit pipelined SAR ADC in 40 nm digital CMOS is presented. Each ADC channel consists of a 6b coarse SAR, a dynamic residue amplifier and a 7b fine SAR with a total of two bits of redundancy. Calibration is leveraged to adjust the uncertain gain of the chosen residue amplifier and various other non-idealities. The ADC achieves a peak SNDR of 62 dB at 10 MS/s, and 56 dB for a Nyquist input at 250 MS/s. The low frequency energy per conversion step ranges from 7 fJ at 10 MS/s to 10 fJ at 250 MS/s.

Keywords

CMOS analogue integrated circuits; CMOS digital integrated circuits; amplifiers; analogue-digital conversion; calibration; redundancy; ADC channel; Nyquist input; calibration; conversion step; digital CMOS; dynamic residue amplifier; energy 7 fJ to 10 fJ; interleaved fully dynamic pipelined SAR ADC; low frequency energy; peak SNDR; power 1.7 mW; redundancy; size 40 nm; CMOS integrated circuits; Calibration; Capacitance; Switches; Transistors; Analog–digital conversion; CMOS technology; analog–digital integrated circuits; calibration;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2012.2217873

Filename

6332545