A Nonbinary LDPC Decoder Architecture With Adaptive Message Control

A new decoder architecture for nonbinary low-density paritycheck (LDPC) codes is presented in this paper to reduce the hardware operational complexity in VLSI implementations. The low decoding complexity is achieved by employing adaptive message control (AMC) that dynamically trims the message length of belief information to reduce the amount of memory accesses and arithmetic operations. To implement the proposed AMC, we develop the architecture of a horizontal sequential nonbinary LDPC decoder. Key components in the architecture have been designed with the consideration of variable message lengths to leverage the benefit of the proposed AMC. Simulation results demonstrate that the proposed nonbinary LDPC decoder architecture can significantly reduce hardware operations and power consumption as compared with existing work with negligible performance degradation.