Progress and Prospects of Spin Transfer Torque Random Access Memory

Author

Chen, E. ; Apalkov, D. ; Driskill-Smith, A. ; Khvalkovskiy, A. ; Lottis, D. ; Moon, K. ; Nikitin, V. ; Ong, A. ; Tang, X. ; Watts, S. ; Kawakami, R. ; Krounbi, M. ; Wolf, S.A. ; Poon, S.J. ; Lu, J.W. ; Ghosh, A.W. ; Stan, M. ; Butler, W. ; Mewes, Tim ; Gu

Author_Institution

Grandis, Milpitas, CA, USA

Volume

48

Issue

11

fYear

2012

Firstpage

3025

Lastpage

3030

Abstract

We report our progress on material improvement, device design, wafer processing, integration with CMOS, and testing of STT-RAM memory chips at 54 nm node with cell sizes of 14 and 28 F² (F=54 nm). A dual tunnel barrier MTJ structure was found to have lower and more symmetric median spin transfer torque writing switching currents, and much tighter parallel to antiparallel switching current distribution. In-plane MTJ devices write endurance data, read and write soft error rates data and simulation fits, and solutions to the long write error rate tail at fast write speeds are discussed.

Keywords

CMOS memory circuits; current distribution; integrated circuit design; integrated circuit testing; magnetic storage; magnetic tunnelling; magnetoelectronics; random-access storage; CMOS integration; STT-RAM memory chip testing; antiparallel switching current distribution; device design; dual tunnel barrier MTJ structure; in-plane MTJ devices; read-write soft error rate data; size 54 nm; spin transfer torque random access memory; symmetric median spin transfer torque writing switching currents; wafer processing; write error rate tail; Magnetic tunneling; Performance evaluation; Random access memory; Switches; Thermal stability; Torque; Writing; Magnetic tunnel junction (MTJ); STT-MRAM; STT-RAM; nonvolatile memory (NVM); spin transfer torque (STT);

fLanguage

English

Journal_Title

Magnetics, IEEE Transactions on

Publisher

ieee

ISSN

0018-9464

Type

jour

DOI

10.1109/TMAG.2012.2198451

Filename

6332660