Title :
Energy reduction techniques for H.264 deblocking filter hardware
Author :
Adibelli, Yusuf ; Parlak, Mehmet ; Hamzaoglu, Ilker
Author_Institution :
Dept. of Electron. Eng., Sabanci Univ., Istanbul, Turkey
fDate :
8/1/2011 12:00:00 AM
Abstract :
In this paper, we propose pixel equality and pixel similarity based techniques for reducing the amount of computations performed by H.264 Deblocking Filter (DBF) algorithm, and therefore reducing the energy consumption of H.264 DBF hardware. These techniques avoid unnecessary calculations in H.264 DBF algorithm by exploiting the equality and similarity of the pixels used in DBF equations. The proposed techniques reduce the amount of addition and shift operations performed by H.264 DBF algorithm up to 52% and 67% respectively with a small comparison overhead. The pixel equality based technique does not affect PSNR. The pixel similarity based technique does not affect the PSNR for some video frames, but it decreases the PSNR slightly for some video frames. We also implemented an efficient H.264 DBF hardware including the proposed techniques using Verilog HDL. The proposed pixel equality and pixel similarity based techniques reduced the energy consumption of this H.264 DBF hardware up to 35% and 39%, respectively. Therefore, they can be used in portable consumer electronics products that require real-time video compression.
Keywords :
data compression; filters; hardware description languages; video coding; H.264 DBF hardware; H.264 deblocking filter hardware; PSNR; Verilog HDL; energy consumption; energy reduction technique; pixel equality; pixel similarity; real-time video compression; video frame; Algorithm design and analysis; Equations; Filtering; Filtering algorithms; Hardware; Mathematical model; Prediction algorithms; Deblocking Filter; Energy Reduction; FPGA; H.264; Hardware Implementation;
Journal_Title :
Consumer Electronics, IEEE Transactions on
DOI :
10.1109/TCE.2011.6018900