Effective Search Point Reduction Algorithm and its VLSI Design for HDTV H.264/AVC Variable Block Size Motion Estimation

Variable block size motion estimation (VBSME) in H.264/AVC has greatly led to achieve an optimal inter frame encoding. However, the computation burden of the VBSME becomes the bottleneck of the H.264/AVC encoders. The conventional architecture in hardware realization is hard to adopt a fast software algorithm suitable to reduce the VBSME computation burden. Therefore, this paper presents a search point reduction (SPR) algorithm with an efficient hardware design, able to decrease the motion estimation time while maintaining the coding performance of H.264. The effectiveness of the proposed method is compared with those of existing methods with respect to chip area, operation frequency, and throughput rate. The proposed SPR algorithm increases the coding speed by around 90%; with a peak signal-to-noise ratio drop of less than 0.1 dB than that achieved by the JM reference software. The proposed SPR algorithm can operate at 200 MHz with 191 k gate count, which supports high-definition television 1280  720 format.