Integration of Tantalum Pentoxide Capacitors With Through-Silicon Vias

Metal filled through-silicon vias (TSVs) allow devices to be connected using a 3-D approach. Optimizing and refining this technology has been a focus for the semiconductor industry the past few years because of the need for novel integrated circuit (IC) packages that address the issues associated with increased functionality and performance while reducing size and costs for a growing number of defense and consumer electronic applications. Vertical interconnection using TSV technology has emerged as a convenient way to improve system performance. Integration of decoupling capacitors with TSVs represents an attractive alternative to conventional 2-D layouts to achieve miniaturization and increased density. Decoupling capacitors can be brought in close proximity to the active elements, thereby reducing their parasitic inductance and allowing higher clock rates. In this paper, capacitors with anodized tantalum oxide dielectric were integrated with TSVs and their performance was evaluated. Fabricated capacitors were found to exhibit satisfactory electrical properties before and after TSV processing although some changes in their properties were observed. The performance of these capacitors for applications such as high speed decoupling capacitors was evaluated by measuring resonant frequency, parasitic inductance, and parasitic resistance.