DocumentCode :
1322734
Title :
A VLSI modulo m multiplier
Author :
Alia, Giuseppe ; Martinelli, Enrico
Author_Institution :
Fac. of Eng., Pisa Univ., Italy
Volume :
40
Issue :
7
fYear :
1991
fDate :
7/1/1991 12:00:00 AM
Firstpage :
873
Lastpage :
878
Abstract :
A novel method to compute the exact digits of the modulo m product of integers is proposed, and a modulo m multiply structure is defined. Such a structure can be implemented by means of a few fast VLSI binary multipliers, and a response time of about 150-200 ns to perform modular multiplications with moduli up to 32767 can be reached. A comparison to ROM-based structures is also provided. The modular multiplier has been evaluated asymptotically, according to the VLSI complexity theory, and it turned out to be an optimal design. This structure can be used to implement a residue multiplier in arithmetic structures using residue number systems (RNSs). The complexity of this residue multiplier has been evaluated and lower complexity figures than for ROM-based multiply structures have been obtained under several hypotheses on RNS parameters
Keywords :
VLSI; computational complexity; digital arithmetic; VLSI; modular multiplications; modulo m multiplier; residue multiplier; Automatic testing; Complexity theory; Counting circuits; Delay; Error analysis; Polynomials; Propulsion; Registers; State feedback; Very large scale integration;
fLanguage :
English
Journal_Title :
Computers, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9340
Type :
jour
DOI :
10.1109/12.83626
Filename :
83626
Link To Document :
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