DocumentCode :
1322759
Title :
A modular fault-tolerant binary tree architecture with short links
Author :
Singh, Adit D. ; Youn, Hee Yong
Author_Institution :
Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
Volume :
40
Issue :
7
fYear :
1991
fDate :
7/1/1991 12:00:00 AM
Firstpage :
882
Lastpage :
890
Abstract :
The authors present a novel modular fault-tolerant binary tree architecture which is shown to be more effective in overcoming both operational faults and fabrication defects than earlier approaches. Furthermore, for practical size trees of up to eight levels, it is shown how the proposed design can be efficiently load out in VLSI with very short interconnections. Thus, the design is suitable for monolithic implementation of a large binary tree architectures. For board level multichip designs, a hybrid scheme, combining the new design with the SOFT approach, is presented. It shows better reliability than either design alone
Keywords :
computer architecture; fault tolerant computing; SOFT approach; VLSI; binary tree architecture; board level multichip designs; fabrication defects; fault-tolerant; operational faults; Automatic testing; Binary trees; Circuit faults; Circuit testing; Computer science; Delay; Fabrication; Fault tolerance; Integrated circuit interconnections; Very large scale integration;
fLanguage :
English
Journal_Title :
Computers, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9340
Type :
jour
DOI :
10.1109/12.83628
Filename :
83628
Link To Document :
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