Title :
A BiCMOS technology with 660-MHz vertical p-n-p transistor for analog/digital ASICs
Author :
Soejima, Katsumoto ; Shida, Akira ; Koga, Hiroshi ; Ukai, Junnichi ; Sata, Hiroshi ; Hirata, Masaki
Author_Institution :
NEC Corp., Kanagawa, Japan
fDate :
4/1/1990 12:00:00 AM
Abstract :
A fully complementary BiCMOS technology based on a 2-μm process designed for 12-V analog/digital applications is described. In this technology, a triple diffused vertical p-n-p transistor and n-p-n bipolar and CMOS devices are integrated in a single chip. A transition frequency of 660 MHz and a collector-to-emitter breakdown voltage of over 15 V have been obtained for the collector-isolated p-n-p transistor by adding only one extra mask to a conventional 2-μm BiCMOS process. The total number of masks is 20 with double-layer metallization. A unity gain frequency of 52 MHz and a DC gain of 85 dB have been obtained for a single-supply operational amplifier with a vertical p-n-p first stage. The propagation delay time for a CMOS two-NAND gate was 1.27 ns driving three loads and 3 mm of metal
Keywords :
BIMOS integrated circuits; application specific integrated circuits; digital integrated circuits; integrated circuit technology; linear integrated circuits; operational amplifiers; 1.27 ns; 12 V; 2 micron; 52 MHz; 660 MHz; 85 dB; BiCMOS technology; CMOS devices; DC gain; collector-isolated p-n-p transistor; collector-to-emitter breakdown voltage; double-layer metallization; extra mask; mixed analog digital ASICs; mixed mode ASICs; n-p-n bipolar; propagation delay time; single-supply operational amplifier; transition frequency; triple diffused vertical p-n-p transistor; unity gain frequency; Analog circuits; Application specific integrated circuits; BiCMOS integrated circuits; CMOS logic circuits; CMOS technology; Costs; Fabrication; Frequency; Integrated circuit technology; Logic circuits;
Journal_Title :
Solid-State Circuits, IEEE Journal of
