DocumentCode :
1323043
Title :
A 20-MHz Bandwidth Continuous-Time Sigma-Delta Modulator With Jitter Immunity Improved Full Clock Period SCR (FSCR) DAC and High-Speed DWA
Author :
Jo, Jun-Gi ; Noh, Jinho ; Yoo, Changsik
Author_Institution :
SmartPHY Inc., Seoul, South Korea
Volume :
46
Issue :
11
fYear :
2011
Firstpage :
2469
Lastpage :
2477
Abstract :
A 20-MHz bandwidth continuous-time (CT) sigma-delta modulator (SDM) with third-order active-RC loop filter and 4-bit quantizer is implemented in a 0.13-μm CMOS process. The immunity to clock jitter is greatly improved by employing full clock period switched-capacitor-resistor (FSCR) digital-to-analog converter (DAC) for feedback. A new data weighted averaging (DWA) technique is developed to remove the timing bottleneck at 640 MHz clock frequency. The CT SDM achieves 63.9 dB peak signal-to-noise-and-distortion ratio (SNDR) and 68 dB dynamic range (DR) which decreases by only 2.3 dB when the RMS jitter of the 640 MHz clock is 15.6 ps. The power consumption is 58 mW from a 1.2-V supply.
Keywords :
CMOS integrated circuits; active filters; clocks; digital-analogue conversion; low-power electronics; sigma-delta modulation; switched capacitor filters; CMOS process; DAC; RMS jitter; bandwidth 20 MHz; continuous-time sigma-delta modulator; data weighted averaging; digital-to-analog converter; frequency 640 MHz; full clock period SCR; high-speed DWA; jitter immunity; power 58 mW; power consumption; quantizer; signal-to-noise-and-distortion ratio; size 0.13 mum; switched-capacitor-resistor; third-order active-RC loop filter; time 15.6 ps; voltage 1.2 V; Clocks; Jitter; Modulation; Noise; Optical signal processing; Power capacitors; Thyristors; Clock jitter; continuous-time sigma-delta modulator; data weighted averaging; switched-capacitor resistor (SCR) feedback;
fLanguage :
English
Journal_Title :
Solid-State Circuits, IEEE Journal of
Publisher :
ieee
ISSN :
0018-9200
Type :
jour
DOI :
10.1109/JSSC.2011.2164296
Filename :
6021342
Link To Document :
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