A Digitized Replica Bitline Delay Technique for Random-Variation-Tolerant Timing Generation of SRAM Sense Amplifiers

Author

Niki, Yusuke ; Kawasumi, Atsushi ; Suzuki, Azuma ; Takeyama, Yasuhisa ; Hirabayashi, Osamu ; Kushida, Keiichi ; Tachibana, Fumihiko ; Fujimura, Yuki ; Yabe, Tomoaki

Author_Institution

Center for Semicond. R&D, Toshiba Corp., Kawasaki, Japan

Volume

46

Issue

11

fYear

2011

Firstpage

2545

Lastpage

2551

Abstract

A digitized replica bitline delay technique has been proposed for random-variation-tolerant timing generation of static random access memory (SRAM) sense amplifiers (SA). The timing variation of SA attributable to the random variation of transistor threshold voltage (V_TH) is reduced by a sufficient count of replica cells, and replica bitline delay is digitized and multiplied to adjust it to the target timing for SA. The variation of the generated timing was 41% smaller than that with a conventional technique and cycle time was reduced 20% at the supply voltage (V_DD) of 0.6 V in 40 nm CMOS technology with this scheme.

Keywords

CMOS memory circuits; SRAM chips; amplifiers; delay circuits; timing circuits; CMOS technology; SRAM sense amplifier; digitized replica bitline delay technique; random variation tolerant timing generation; replica cells; size 40 nm; static random access memory; supply voltage; timing variation; transistor threshold voltage variation; voltage 0.6 V; CMOS integrated circuits; CMOS technology; Delay; Monte Carlo methods; Random access memory; Threshold voltage; Random variation; replica bitline delay; sense amplifier (SA); static random access memory (SRAM); timing generation;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2011.2164294

Filename

6021343