Title :
Design for test technique for increasing the resolution of supply current monitoring in analogue circuits
Author :
Chalk, C.D. ; Zwolinski, M.
Author_Institution :
Dept. of Electron. & Comput. Sci., Southampton Univ., UK
fDate :
10/9/1997 12:00:00 AM
Abstract :
A design-for-test (DFT) technique for analogue circuits is proposed which splits all high current transistors into two. This technique reduces the fault-masking effects of the fault-free parts of the circuit, giving a potential fault cover of over 99%. Other advantages are the small area overhead and a low performance penalty
Keywords :
analogue integrated circuits; design for testability; integrated circuit design; integrated circuit testing; monitoring; DFT technique; analogue circuits; design-for-test technique; fault coverage; resolution; supply current monitoring;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19971174
