• DocumentCode
    1323124
  • Title

    Reduction of power consumption during test application by test vector ordering [VLSI circuits]

  • Author

    Girard, P. ; Landrault, C. ; Pravossoudovitch, S. ; Severac, D.

  • Author_Institution
    Lab. d´´Inf. de Robotique et de Microelectron. de Montpellier, France
  • Volume
    33
  • Issue
    21
  • fYear
    1997
  • fDate
    10/9/1997 12:00:00 AM
  • Firstpage
    1752
  • Lastpage
    1754
  • Abstract
    The authors address the problem of testing VLSI circuits without exceeding their power ratings during testing. The proposed approach is based on re-ordering test vectors in a test sequence to minimise the switching activity of the circuit during test application. Results or experiments are presented which show a power reduction in the range 7.5-55.8% during test application
  • Keywords
    VLSI; automatic testing; integrated circuit testing; VLSI circuit testing; power consumption reduction; power ratings; switching activity minimisation; test application; test sequence; test vector ordering;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:19971225
  • Filename
    633370
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1323124