Title :
Indirectly-compared cache tag memory using a shared tag in a TLB
Author :
Lee, Yonghwan ; Lee, Taeyoung ; An, Sangjun ; Lee, Yongsurk
Author_Institution :
Dept. of Electron. Eng., Yonsei Univ., Seoul, South Korea
fDate :
10/9/1997 12:00:00 AM
Abstract :
A shared tag by which both translation lookaside buffers (TLBs) and caches can be accessed is presented. This architecture reduces the chip area of conventional cache tags and also improves the speed of cache systems. To validate the proposed architecture, the authors measured both the area and speed based on VLSI circuits
Keywords :
VLSI; cache storage; integrated memory circuits; memory architecture; VLSI circuits; architecture; indirectly-compared cache tag memory; shared tag; translation lookaside buffers;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19971159
