DocumentCode
1323446
Title
Algorithmic synthesis of MVL functions for CCD implementation
Author
Abd-El-Barr, Mostafa H. ; Vranesic, Zvonko G. ; Zaky, Safwat G.
Author_Institution
Dept. of Comput. Sci., Saskatchewan Univ., Saskatoon, Sask., Canada
Volume
40
Issue
8
fYear
1991
fDate
8/1/1991 12:00:00 AM
Firstpage
977
Lastpage
986
Abstract
Algorithms for synthesis of four-valued one- and two-variable functions for CCD (charge coupled device) implementation are proposed. One-variable synthesis is based on the observation that the cost of a realization of a function f (x ) increases in the presence of breaks, or negative transitions, in the value of f as x increases. The function is decomposed to minimize the number of such transitions. Two-variable functions are synthesized as a sum of products of literals, taking advantage of literals that are easily implemented in CCD technology. It is concluded that the proposed algorithms perform better than those published previously
Keywords
charge-coupled devices; logic circuits; logic design; many-valued logics; CCD implementation; MVL functions; algorithmic synthesis; literals; sum of products; Area measurement; Charge coupled devices; Circuits; Cost function; Logic devices; Logic functions; Logic gates; Multivalued logic; Potential well; Semiconductor device measurement;
fLanguage
English
Journal_Title
Computers, IEEE Transactions on
Publisher
ieee
ISSN
0018-9340
Type
jour
DOI
10.1109/12.83641
Filename
83641
Link To Document