Title :
Highly parallel architecture for the least mean squares (LMS) algorithm
Author :
Lapointe, M. ; Huu Tue Huynh ; Fortier, Paul
Author_Institution :
Dept. de Genie Electr., Fac. des Sci. et de Genie, Laval Univ., Que., Canada
fDate :
7/1/1991 12:00:00 AM
Abstract :
A fast digital implementation for the least mean squares algorithm is proposed. The high concurrency of its structure allows for high processing speed with a sampling period of O(log N), where N is the number of filter taps. Chip area is minimized by the use of serial-parallel multipliers. In these multipliers, which use redundant arithmetic, the serial variables are transferred digit by digit, the most significant first.
Keywords :
computerised signal processing; digital filters; least squares approximations; mathematics computing; parallel architectures; LMS; chip area minimization; fast digital implementation; filter taps; high processing speed; highly parallel architecture; least mean squares algorithm; redundant arithmetic; sampling period; serial-parallel multipliers; signal processing; Convergence; Convolution; Gold; Least squares approximations; Multiplexing; Pipelines; Signal processing algorithms;
Journal_Title :
Electrical and Computer Engineering, Canadian Journal of
DOI :
10.1109/CJECE.1991.6592939
