VLSI architectures for multidimensional transforms

The authors propose a family of VLSI architectures with area-time tradeoffs for computing (N×N× . . . ×N) d-dimensional linear separable transforms. For fixed-precision arithmetic with b bits, the architectures have an area A=O(N^d+2a) and computation time T=O(dN^d/2-ab ), and achieve the AT² bound of AT²=O(n²b ²) for constant d, where n=N^d and O<a⩽d/2