Single-polarity dual-rail logic

Static CMOS circuit techniques are widely used for processor design. The authors introduce an add-on technique for high-speed static circuit realisation. The underlying processes of this technique, a time-shifting process and a collision process, are described and the performance of the resulting circuitry is compared with that of the conventional version. The new technique, which utilises a single polarity signal on a separate path, achieves ~15% delay reduction compared with the conventional static CMOS design