Title :
Auxiliary Specifications for Context-Sensitive Monitoring of AMS Assertions
Author :
Mukherjee, Sayan ; Dasgupta, Parthasarathi ; Mukhopadhyay, Saibal
Author_Institution :
Dept. of Comput. Sci. & Eng., Indian Inst. of Technol. Kharagpur, Kharagpur, India
Abstract :
As research on developing assertion languages for the analog and mixed-signal (AMS) domain gains in momentum, it is increasingly being felt that extensions of existing assertion languages like property specification language and SystemVerilog assertions into the AMS domain are not adequate for expressing the analog design intent. This is largely due to the intricacy of the analog behavioral intent which cannot be captured purely in terms of logic. In this paper, we show that by using auxiliary forms of formal specifications such as abstract state machines and real-valued functions, called auxiliary functions, as references for AMS assertions, it becomes possible to model complex AMS behavioral properties. In addition, we present complexity results for the satisfiability problem of such specifications. This approach leverages the growing adoption of AMS behavioral modeling in the industry. This paper also shows that the use of auxiliary state machines allows us to separate out the scope of different analog assertions leading to significant performance gains in the assertion checking overhead.
Keywords :
computability; formal specification; mixed analogue-digital integrated circuits; specification languages; temporal logic; AMS assertions; SystemVerilog assertions; abstract state machines; analog and mixed-signal domain gains; analog behavioral intent; assertion checking overhead; assertion languages; auxiliary functions; auxiliary specifications; context-sensitive monitoring; formal specifications; property specification language; real-valued functions; satisfiability problem; temporal logic; Complexity theory; Context; Industries; Regulators; Semantics; Syntactics; Voltage control; Auxiliary functions; auxiliary state machines; satisfiabiliy; temporal logic; verification;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
DOI :
10.1109/TCAD.2011.2155065