DocumentCode
1324136
Title
A Halting Algorithm to Determine the Existence of the Decoder
Author
ShengYu Shen ; Ying Qin ; Liquan Xiao ; Kefei Wang ; Jianmin Zhang ; Sikun Li
Author_Institution
Sch. of Comput., Nat. Univ. of Defense Technol., Changsha, China
Volume
30
Issue
10
fYear
2011
Firstpage
1556
Lastpage
1563
Abstract
Complementary synthesis automatically synthesizes the decoder circuit of an encoder. It determines the existence of the decoder by checking whether the encoder´s input can be uniquely determined by its output. However, this algorithm will not halt if the decoder does not exist. To solve this problem, a novel halting algorithm is proposed. For every path of the encoder, this algorithm first checks whether the encoder´s input can be uniquely determined by its output. If yes, the decoder exists; otherwise, this algorithm checks if this path contains loops, which can be further unfolded to prove the non-existence of the decoder for all those longer paths. To illustrate its usefulness and efficiency, this algorithm has been run on several complex encoders, including PCI-E and Ethernet. Experimental results indicate that this algorithm always halts properly by distinguishing correct encoders from incorrect ones, and it is more than three times faster than previous ones.
Keywords
computability; decoding; network synthesis; Ethernet; PCI-E; decoder circuit synthesis; encoder; halting algorithm; Algorithm design and analysis; Benchmark testing; Cost accounting; Decoding; Manganese; Runtime; Signal processing algorithms; Complementary synthesis; halting algorithm;
fLanguage
English
Journal_Title
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher
ieee
ISSN
0278-0070
Type
jour
DOI
10.1109/TCAD.2011.2159792
Filename
6022015
Link To Document