DocumentCode :
1324194
Title :
Design of fast motion estimation algorithm based on hardware consideration
Author :
He, Zhongli ; Liou, Ming L.
Author_Institution :
Dept. of Electr. & Electron. Eng., Hong Kong Univ. of Sci. & Technol., Hong Kong
Volume :
7
Issue :
5
fYear :
1997
fDate :
10/1/1997 12:00:00 AM
Firstpage :
819
Lastpage :
823
Abstract :
Most fast block-matching motion estimation (BMME) algorithms are designed to minimize the search positions (or checking points) in a given search range in order to speed up the computation. In this paper, we introduce a fast BMME algorithm based on the consideration of hardware implementation. We use a one-dimensional (1-D) systolic array as the basic computing engine. In order to utilize this engine efficiently, we process several adjacent checking points, called checking vector, simultaneously. We propose a checking-vector-based search strategy and show that it can achieve a better algorithmic performance and can be very cost-effective in terms of hardware implementation for low bit-rate video applications
Keywords :
VLSI; image matching; motion estimation; search problems; systolic arrays; video coding; VLSI architecture; adjacent checking points; checking-vector-based search strategy; fast block-matching motion estimation algorithm; hardware implementation; low bit-rate video applications; one-dimensional systolic array; video coding; Algorithm design and analysis; Costs; Engines; Hardware; Helium; Motion estimation; Systolic arrays; Telecommunications; Very large scale integration; Video coding;
fLanguage :
English
Journal_Title :
Circuits and Systems for Video Technology, IEEE Transactions on
Publisher :
ieee
ISSN :
1051-8215
Type :
jour
DOI :
10.1109/76.633505
Filename :
633505
Link To Document :
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