A 16-b 160-kHz CMOS A/D converter using sigma-delta modulation

Author

Rebeschini, Mike ; Van Bavel, Nicholas R. ; Rakers, Patrick ; Greene, Robert ; Caldwell, James ; Haug, John R.

Author_Institution

Motorola Inc., Schaumburg, IL, USA

Volume

25

Issue

2

fYear

1990

fDate

4/1/1990 12:00:00 AM

Firstpage

431

Lastpage

440

Abstract

The design and measured performance of a third-order sigma-delta analog-to-digital (A/D) converter sampling at 10.24 MHz that achieves a 91-dB signal-to-noise-plus-distortion ratio (RMS/RMS) with a 160-kHz output rate are discussed. The converter consists of three cascaded first-order sigma-delta modulators and a fourth-order comb decimation filter. A special autozeroed integrator having low pole error is required to achieve the 10.24-MHz sampling rate and high S/N. The modulator is implemented with fully differential switched-capacitor circuits and is manufactured using a 1.5-μm double-metal double-poly CMOS process

Keywords

CMOS integrated circuits; analogue-digital conversion; 1.5 micron; 10.24 MHz; 16 bit; 160 kHz; 91 dB; A/D converter; CMOS; CMOS process; SNR; autozeroed integrator; cascaded first-order sigma-delta modulators; differential switched-capacitor circuits; double-metal; double-poly; fourth-order comb decimation filter; output rate; performance; sampling rate; sigma-delta modulation; signal-to-noise-plus-distortion ratio; third-order sigma-delta ADC; Analog-digital conversion; Bandwidth; CMOS process; Circuits; Delta-sigma modulation; Digital signal processing; Low pass filters; Sampling methods; Semiconductor device noise; Signal resolution;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.52167

Filename

52167