Mixed-mode simulation of DX trap-induced slow transient effects on AlGaAs/GaAs HEMT inverters

A mixed level device and circuit simulation was performed to analyze DX trap-induced slow transient effects on the performance degradation of AlGaAs/GaAs high electron mobility transistor (HEMT) circuits. The variation of the output pulsewidth and the hysteretic characteristics of the input-output voltage transfer function in direct-coupled FET logic (DCFL) HEMT inverters have been simulated. In the model, a DX trap rate equation is calculated in the AlGaAs layer. The self-consistent Schrodinger and Poisson equations are solved numerically at each cross section of a device. A two-region Grebene-Ghandhi model is used to derive the I-V characteristics. The simulation confirms that the output pulse broadening and narrowing effects in string cascaded DCFL HEMT inverters are a consequence of the inverter voltage transfer function shift caused by deep traps