• DocumentCode
    1325663
  • Title

    An evaluation of parallel simulated annealing strategies with application to standard cell placement

  • Author

    Chandy, John A. ; Kim, Sungho ; Ramkumar, Barathram ; Parkes, Steven ; Banerjee, Prithviraj

  • Author_Institution
    Sierra Vista Res., Los Gatos, CA, USA
  • Volume
    16
  • Issue
    4
  • fYear
    1997
  • fDate
    4/1/1997 12:00:00 AM
  • Firstpage
    398
  • Lastpage
    410
  • Abstract
    Simulated annealing, a methodology for solving combinatorial optimization problems, is a very computationally expensive algorithm and, as such, numerous researchers have undertaken efforts to parallelize it. In this paper, we investigate three of these parallel simulated annealing strategies when applied to standard cell placement, specifically the TimberWolfSC placement tool. We have examined a parallel moves strategy, as well as two new approaches to parallel cell placement-multiple Markov chains and speculative computation. These algorithms have been implemented in ProperPLACE, our parallel cell placement application, as part of the ProperCAD II project. We have constructed ProperPLACE so that it is portable across a wide range of parallel architectures. Our parallel moves algorithm uses novel approaches to dynamic message sizing, message prioritization, and error control. We show that parallel moves and multiple Markov chains are effective approaches to parallel simulated annealing when applied to TimberWolfSC, yet speculative computation is wholly inadequate
  • Keywords
    Markov processes; cellular arrays; circuit layout CAD; circuit optimisation; logic CAD; parallel algorithms; simulated annealing; ProperCAD II project; ProperPLACE; TimberWolfSC placement tool; combinatorial optimization problems; dynamic message sizing; error control; message prioritization; multiple Markov chains; parallel moves strategy; parallel simulated annealing strategies; speculative computation; standard cell placement; Buildings; Computational modeling; Concurrent computing; Databases; Error correction; Optimization methods; Parallel algorithms; Parallel architectures; Simulated annealing; Sun;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/43.602476
  • Filename
    602476