Efficient conversion algorithms for long-word-length binary logarithmic numbers and logic implementation

The logarithmic number system is an attractive alternative to the conventional number systems when data need to be manipulated at very high rate over a wide data range. However, the major problem is deriving logarithms and antilogarithms quickly and accurately enough to allow conversions to and from the conventional number representations. The paper presents efficient algorithms that convert the conventional binary numbers to binary logarithmic numbers, where long-word-length numbers are considered. The conversion problem can be formulated as a division-like problem. This implementation adopts the modified SRT division scheme so that the full-length addition/subtraction operations can be avoided. The speed performance of the logic implementation has been evaluated based on the TSMC 0.8 μm SPDM CMOS process. Results show that, for the numbers in IEEE double precision format with 53 bits in the fractional part and with an additional seven guarding digits to maintain the accuracy, it takes about 0.4 μs to convert a number, where the ROM table size is 128-by-60 bits, or 7.5 kbits. The speed performances of the logic implementation for long-word-length, such as 128 bits, 256 bits, and 512 bits, are also evaluated in terms of the required ROM table size and delay time. The algorithm can handle any arbitrary word length, with the required accuracy, at reasonable speed