DocumentCode
1326106
Title
An array architecture for fast computation of discrete Hartley transform
Author
Dhar, Anindya S. ; Banerjee, Swapna
Author_Institution
Dept. of Electron. & Electr. Commun. Eng., Indian Inst. of Technol., Kharagpur, India
Volume
38
Issue
9
fYear
1991
fDate
9/1/1991 12:00:00 AM
Firstpage
1095
Lastpage
1098
Abstract
Fast computation of the discrete Hartley transform (DHT) may be performed by employing a set of linear arrays of Givens rotors. It is shown that the interconnections between the linear arrays can be realized in a regular fashion governed by a permutation cycle that can be determined by simple arithmetic involving a primitive root of the transform length. A suitable implementation of the Givens rotor with add/subtract units and hard-wired shifters is also suggested
Keywords
computerised signal processing; mathematics computing; parallel architectures; transforms; Givens rotors; add/subtract units; array architecture; discrete Hartley transform; hard-wired shifters; linear arrays; Circuit stability; Circuit testing; Computer architecture; DH-HEMTs; Digital filters; Discrete transforms; Multidimensional systems; Polynomials; Stability analysis; Sufficient conditions;
fLanguage
English
Journal_Title
Circuits and Systems, IEEE Transactions on
Publisher
ieee
ISSN
0098-4094
Type
jour
DOI
10.1109/31.83883
Filename
83883
Link To Document