DocumentCode
1326208
Title
A 1.2 V 12.8 GB/s 2 Gb Mobile Wide-I/O DRAM With 4 
128 I/Os Using TSV Based Stacking
Author
Kim, Jung-Sik ; Oh, Chi Sung ; Lee, Hocheol ; Lee, Donghyuk ; Hwang, Hyong Ryol ; Hwang, Sooman ; Na, Byongwook ; Moon, Joungwook ; Kim, Jin-Guk ; Park, Hanna ; Ryu, Jang-Woo ; Park, Kiwon ; Kang, Sang Kyu ; Kim, So-Young ; Kim, Hoyoung ; Bang, Jong-Min ;
Author_Institution
Memory Div., Samsung Electron., Co., Ltd., Hwasung, South Korea
Volume
47
Issue
1
fYear
2012
Firstpage
107
Lastpage
116
Abstract
A 1.2 V 1 Gb mobile SDRAM, having 4 channels with 512 DQ pins has been developed with 50 nm technology. It exhibits 330.6 mW read operating power during 4 channel operation, achieving 12.8 GB/s data bandwidth. Test correlation techniques to verify functions through micro bumps and test pads have been developed. Block based dual period refresh scheme is applied to reduce self refresh current with minimum chip size burden. Stacking of 2 dies with 7.5 μm diameter and 40 μm pitch TSVs has been fabricated and tested, which results in 76% overall package yield without difference in performances between top and bottom die.
Keywords
DRAM chips; input-output programs; three-dimensional integrated circuits; 512 DQ pins; bit rate 12.8 Gbit/s; micro bumps; mobile wide-I/O DRAM; pitch TSV based stacking; size 50 nm; size 7.5 mum; test correlation techniques; voltage 1.2 V; CMOS integrated circuits; CMOS memory circuits; DRAM chips; Random access memory; SDRAM; Silicon; Through-silicon vias; CMOS memory integrated circuits; DRAM chips; through-silicon vias;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/JSSC.2011.2164731
Filename
6025219
Link To Document