Title :
Reducing Power in All Major CAM and SRAM-Based Processor Units via Centralized, Dynamic Resource Size Management
Author :
Homayoun, Houman ; Sasan, Avesta ; Gaudiot, Jean-Luc ; Veidenbaum, Alex
Author_Institution :
Comput. Sci., UCI, Irvine, CA, USA
Abstract :
Power minimization has become a primary concern in microprocessor design. In recent years, many circuit and micro-architectural innovations have been proposed to reduce power in many individual processor units. However, many of these prior efforts have concentrated on the approaches which require considerable redesign and verification efforts. Also it has not been investigated whether these techniques can be combined. Therefore a challenge is to find a centralized and simple algorithm which can address power issues for more than one unit, and ultimately the entire chip and comes with the least amount of redesign and verification efforts, the lowest possible design risk and the least hardware overhead. This paper proposes such a centralized approach that attempts to simultaneously reduce power in processor units with highest dissipation: reorder buffer, instruction queue, load/store queue, and register files. It is based on an observation that utilization for the aforementioned units varies significantly, during cache miss period. Therefore we propose to dynamically adjust the size and thus power dissipation of these resources during such periods. Circuit level modifications required for such resource adaptation are presented. Simulation results show a substantial power reduction at the cost of a negligible performance impact and a small hardware overhead.
Keywords :
SRAM chips; microprocessor chips; CAM; SRAM-based processor unit; cache miss period; centralized resource size management; circuit level modification; dynamic resource size management; individual processor unit; instruction queue; load-store queue; microarchitectural innovation; microprocessor design; power minimization; power reduction; register files; reorder buffer; Benchmark testing; Buffer storage; Complexity theory; Hardware; Logic gates; Monitoring; Registers; CAM unit; Cache miss driven; SRAM unit; centralized low power technique; dynamic resource resizing;
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
DOI :
10.1109/TVLSI.2010.2064185