Title :
Reconfigurable accelerators for combinatorial problems
Author_Institution :
Swiss Fed. Inst. of Technol., Zurich, Switzerland
fDate :
4/1/2000 12:00:00 AM
Abstract :
Reconfigurable accelerators can improve process time on combinatorial problems with fine-grained parallelism. Such problems contain a huge number of logical operations (NOT, AND and OR) that can evaluate simultaneously, a characteristic that varies considerably from problem to problem. Because of this variability, such combinatorial problems are approached using instance-specific reconfiguration-hardware tailored to a specific algorithm and a specific set of input data. Boolean satisfiability (SAT for short) is a common combinatorial problem that exhibits fine-grained parallelism. SAT varies considerably based on the situation. Its solution is thus an ideal candidate for improvements based on instance-specific reconfiguration. In fact, simulation of an instance-specific accelerator show potential speed-ups by a factor of up to 140,000 in execution time over the solution by a software solver. The authors detail the results of their prototype that results an order-of-magnitude speed-up in the execution of difficult satisfiability problems
Keywords :
combinatorial mathematics; computability; mathematics computing; parallel algorithms; parallel architectures; performance evaluation; reconfigurable architectures; special purpose computers; Boolean satisfiability; SAT problem; combinatorial problems; execution time; fine-grained parallelism; hardware circuit; instance-specific reconfiguration; logical operations; process time; reconfigurable accelerators; simultaneous evaluation; speedup; Boolean functions; Clocks; Combinational circuits; Computer architecture; Field programmable gate arrays; Hardware; Logic; Parallel processing; Prototypes; Software prototyping;