Title :
A 250-mW, 8-b, 52-Msamples/s parallel-pipelined A/D converter with reduced number of amplifiers
Author :
Nagaraj, Krishnaswamy ; Fetterman, H. Scott ; Anidjar, Joseph ; Lewis, Stephen H. ; Renninger, Robert G.
Author_Institution :
Lucent Technol. Microelectron., Allentown, PA, USA
fDate :
3/1/1997 12:00:00 AM
Abstract :
A parallel-pipelined A/D converter with an area and power efficient architecture is described. By sharing amplifiers along the pipeline and also completely eliminating the amplifier from the last stage, an 8-b pipeline is realized using just three amplifiers (instead of seven amplifiers with a conventional pipeline architecture). By using two such pipelines in parallel, a 52 Msamples/s prototype A/D converter that is Intended for a switched digital video application has been implemented in a 0.9-μm CMOS technology. The device occupies 15 mm 2 and dissipates 250 mW from a 5 V supply
Keywords :
CMOS integrated circuits; analogue-digital conversion; integrated circuit design; parallel architectures; pipeline processing; video signal processing; 0.9 mum; 250 mW; 5 V; 8 bit; 8-b pipeline; CMOS technology; amplifier sharing; area efficient architecture; high speed ADC; parallel-pipelined A/D converter; power dissipation; power efficient architecture; reduced number of amplifiers; switched digital video application; Analog-digital conversion; CMOS technology; Frequency; Microelectronics; Operational amplifiers; Pipeline processing; Power dissipation; Prototypes; Quadrature amplitude modulation; Sampling methods;
Journal_Title :
Solid-State Circuits, IEEE Journal of
