The modeling, characterization, and design of monolithic inductors for silicon RF IC´s

Author

Long, John R. ; Copeland, Miles A.

Author_Institution

Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada

Volume

32

Issue

3

fYear

1997

fDate

3/1/1997 12:00:00 AM

Firstpage

357

Lastpage

369

Abstract

The results of a comprehensive investigation into the characteristics and optimization of inductors fabricated with the top-level metal of a submicron silicon VLSI process are presented. A computer program which extracts a physics-based model of microstrip components that is suitable for circuit (SPICE) simulation has been used to evaluate the effect of variations in metallization, layout geometry, and substrate parameters upon monolithic inductor performance. Three-dimensional (3-D) numerical simulations and experimental measurements of inductors were also used to benchmark the model accuracy. It is shown in this work that low inductor Q is primarily due to the restrictions imposed by the thin interconnect metallization available in most very large scale integration (VLSI) technologies, and that computer optimization of the inductor layout can be used to achieve a 50% improvement in component Q-factor over unoptimized designs

Keywords

BiCMOS analogue integrated circuits; MMIC; Q-factor; VLSI; circuit analysis computing; circuit layout CAD; circuit optimisation; inductors; integrated circuit layout; integrated circuit metallisation; integrated circuit modelling; lumped parameter networks; microstrip components; BiCMOS technology; GEMCAP; MMIC; SPICE simulation; computer program; design; inductor Q; layout geometry; microstrip components; modeling; monolithic inductors; optimization; physics-based model; rectangular spiral microstrip inductors; submicron silicon VLSI process; substrate parameters; thin interconnect metallization; three-dimensional numerical simulations; top-level metal; Circuits; Computational modeling; Inductors; Metallization; Microstrip components; Physics computing; SPICE; Silicon; Solid modeling; Very large scale integration;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.557634

Filename

557634