Title :
A low voltage SRAM for embedded applications
Author :
Caravella, James S.
Author_Institution :
Semicond. Products Sector, Motorola Inc., Tempe, AZ, USA
fDate :
3/1/1997 12:00:00 AM
Abstract :
A 4-kb SRAM design is presented with functionality of 12 MHz at a supply voltage of 0.9 V with an r.m.s. run power (1 MHz) of 18 μW. The circuit operates at maximum frequency of 40 MHz at a supply voltage of 1.6 V with an rms run power (1 MHz) of 64 μW. The design utilizes a subblocked array architecture as well as selective use of NOR/NAND-based decode logic. The sense amplifier design is a low voltage, glitch-free design to conserve power
Keywords :
CMOS memory circuits; SRAM chips; 0.9 to 1.6 V; 1 to 40 MHz; 18 to 64 muW; 4 kbit; LV operation; NOR/NAND-based decode logic; embedded applications; glitch-free design; low voltage SRAM; sense amplifier design; subblocked array architecture; Batteries; CMOS logic circuits; Energy consumption; FETs; Frequency; Logic arrays; Low voltage; Parasitic capacitance; Random access memory; Threshold voltage;
Journal_Title :
Solid-State Circuits, IEEE Journal of
