Floating-point datapaths with online built-in self speed test

Author

Hagihara, Yasuhiko ; Inui, Shigeto ; Okamoto, Fuyuki ; Nishida, Masato ; Nakamura, Toshihiko ; Yamada, Hachiro

Author_Institution

Microelectron. Res. Labs., NEC Corp., Sagamihara, Japan

Volume

32

Issue

3

fYear

1997

fDate

3/1/1997 12:00:00 AM

Firstpage

444

Lastpage

449

Abstract

This paper describes floating-point (FP) datapaths developed for graphics and simulation applications. The datapaths are fabricated using 0.35 μm CMOS technology and embedded in a 125 MHz, 291 MFLOPS vector pipelined processor for use in supercomputers. A new online test technique has been developed for the purpose of improving reliability under actual operating conditions. The technique makes it easy to detect not only static faults but also delay faults, which has traditionally been difficult

Keywords

CMOS digital integrated circuits; built-in self test; computer testing; floating point arithmetic; integrated circuit testing; logic testing; microprocessor chips; pipeline processing; vector processor systems; 0.35 micron; 125 MHz; 291 MFLOPS; CMOS technology; delay faults; fault detection; floating-point datapaths; graphics and simulation applications; online built-in self speed test; online test technique; reliability; simulation applications; static faults; supercomputers; vector pipelined processor; Automatic testing; CMOS technology; Circuit faults; Circuit simulation; Circuit testing; Delay; Fault detection; Graphics; National electric code; Supercomputers;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.557647

Filename

557647