Toward a general-purpose analog VLSI neural network with on-chip learning

Author

Montalvo, Antonio J. ; Gyurcsik, Ronald S. ; Paulos, John J.

Author_Institution

Ericsson Inc., Research Triangle Park, NC, USA

Volume

8

Issue

2

fYear

1997

fDate

3/1/1997 12:00:00 AM

Firstpage

413

Lastpage

423

Abstract

This paper describes elements necessary for a general-purpose low-cost very large scale integration (VLSI) neural network. By choosing a learning algorithm that is tolerant of analog nonidealities, the promise of high-density analog VLSI is realized. A 64-synapse, 8-neuron proof-of-concept chip is described. The synapse, which occupies only 4900 μm² in a 2-μm technology, includes a hybrid of nonvolatile and dynamic weight storage that provides fast and accurate learning as well as reliable long-term storage with no refreshing. The architecture is user-configurable in any one-hidden-layer topology. The user-interface is fully microprocessor compatible. Learning is accomplished with minimal external support; the user need only present inputs, targets, and a clock. Learning is fast and reliable. The chip solves four-bit parity in an average of 680 ms and is successful in about 96% of the trials

Keywords

CMOS analogue integrated circuits; VLSI; analogue processing circuits; neural chips; neural net architecture; CMOS; VLSI; analog neural chip; dynamic weight storage; neural network; on-chip learning; topology; user-configurable architecture; Circuits; Computer networks; Costs; Network topology; Network-on-a-chip; Neural networks; Neurons; Optical computing; Power engineering computing; Very large scale integration;

fLanguage

English

Journal_Title

Neural Networks, IEEE Transactions on

Publisher

ieee

ISSN

1045-9227

Type

jour

DOI

10.1109/72.557695

Filename

557695